1. Field of the Invention
This invention relates to an apparatus for deriving a synchronizing signal from synchronizing marks pre-formed on an optical or magnetic record carrier and an apparatus for deriving a tracking error signal synchronously from continually formed tracking marks on the record carrier.
2. Description of the Prior Art
A typical apparatus for deriving a synchronizing signal from pre-formed marks is disclosed in U.S. Pat. No. 4,051,527, issued Sept. 27, 1977. The marks are pre-formed periodically along a circular or spiral track on the record carrier, which is formed in a circular disk. From the record carrier in rotation, the marks are reproduced to be a read-out signal by a reading head repeatedly. The read-out signal is then fed to a phase-lock-loop (PLL) composed of a phase comparator, a voltage controlled oscillator (VCO), a count-decoder and a loop filter. The read-out signal is compared with a reference signal in phase by the phase comparator. The phase comparator converts phase difference between the read-out signal and the reference signal to a voltage signal, i.e. a phase error signal. The phase error signal, smoothed by the loop filter, is fed to the voltage controlled oscillator which produces a clock signal, the frequency of which is controlled by the input phase error signal. The count-decoder then produces the reference signal by counting rising edges of the clock signal and yields a pulse in every fixed number of counting.
The clock signal produced in the phase-lock-loop is employed for various functions of a data recording/reproducing system. For example, information data are recorded or reproduced in synchronization with the clock signal.
In the above-described apparatus, however, the phase-lock-loop easily loses the synchronization when the reading head moves outside of the information track. In the prior art, the synchronizing mark is formed along the center-line of the track. When the reading head moves away from the track, e.g. in track jumping operation, the synchronizing mark is not reproduced in enough amplitude. If the amplitude of the read-out signal is too small, a valid phase comparing is no more expected. In that case, the false phase error signal is fed to the phase-lock-loop as a disturbance, which will break the synchronization if lasting in a long period.